The present invention relates to a semiconductor memory device; and, more particularly, to a decoder in a semiconductor memory device.
A semiconductor memory device is an apparatus for storing data and for reading out the stored data. The semiconductor memory device includes a data storage region in which a plurality of unit cells are disposed to store the data and an I/O region in which an I/O circuit is disposed to read out the data stored in the data storage region and to store the data from an external circuit in the data storage region.
The I/O region includes a data input circuit, a data output circuit, an address input circuit and a command input circuit. The data input circuit is to transfer the data from the external circuit to the data storage region in response to a write command. The data output circuit is to output the data stored in the data storage region to the external circuit in response to a read command. The address input circuit is a circuit to input and output address signals which access the unit cells for inputting or outputting the data, respectively, in response to a read command or a write command. The command input circuit is a circuit for interpreting the read command or the write command and then controlling other circuits.
The data storage region has a plurality of banks. The plurality of unit cells which are respectively correspondent to the address signals are included in the bank. Generally, each bank includes a cell block in which a plurality of unit cell are grouped together. Moreover, the decoding circuit is included in the data storage region in order to select one from the plurality of unit cells which corresponds to the input address signal.
FIG. 1 is a block diagram illustrating a semiconductor memory device. Particularly, a decoding circuit of the semiconductor memory device is shown in FIG. 1.
Referring to FIG. 1, the semiconductor memory device includes a plurality of banks 10 and 20 and a decoding circuit 30. Each of the plurality of banks 10 is a region which includes a plurality of unit cells. The decoding circuit 30 includes a predecoder 31 and a main decoder 32 which receive internal address signals BAY<2:7,9> in response to a bank select signal STROBE<0>, decode the inputted signals BAY<2:7,9> and output the decoded signal to the banks 20 and also includes a predecoder 33 and a main decoder 34 which receive the internal address signals BAY<2:7,9> in response to a bank select signal STROBE<1>, decode the inputted signals BAY<2:7,9> and output the decoded signal to the banks 10.
The predecoder 31 is a circuit which first decodes the inputted address signals BAY<2:7,9>. The main decoder 32 is a circuit which again decodes the signal decoded by the predecoder 31. In case of decoding the address signals and outputting the decoded signals to the bank using only one decoder, the decoder becomes so complicated. Therefore, the decoder is classified into the predecoder 31 and main decoder 32 in order to decode the inputted address signals.
FIGS. 2A and 2B are circuit diagrams illustrating the predecoders 31 and 33 illustrated in FIG. 1.
First, as shown in FIG. 2A, the predecoder 33 includes first to fourth internal decoders 33A to 33D. The first internal decoder 33A receives the internal address signals BAY<2:3> in response to a strobe signal STROBE<1> which is activated in response to the activation of the bank 10 and outputs predecoding signals LAY23_B1<2:3> for the bank 10. Here, a bank select signal CAST is a signal which is activated at the time of selecting one from the plurality of banks. A repair signal R<1> is used for addressing a repair territory which is arranged in order to be replaced with a defected normal cell. The internal address signals BAY<2:3> are output signals which are produced by buffering the external address signal in an input buffer. The second internal decoder 33B receives the internal address signals BAY<4> and BAY<5> in response to the bank select signal CAST and outputs first predecoding signals LAY<4:5>. The third internal decoder 33C receives the internal address signals BAY<6> and BAY<7> in response to the bank select signal CAST and outputs second predecoding signals LAY<6:7>. The fourth internal decoder 33D receives the internal address signal BAY<9> in response to the bank select signal CAST and outputs the third predecoding signal LAY<9>.
First, as shown in FIG. 2B, the predecoder 31 includes first to fourth internal decoders 31A to 31D. The first internal decoder 31A receives the internal address signals BAYS<2:3> in response to a strobe signal STROBE<0> which is activated in response to the activation of the bank 20 and outputs predecoding signals LAY23_B0<2:3> for the bank 20. The second internal decoder 31B receives the internal address signals BAY<4> and BAY<5> in response to the bank select signal CAST and outputs first predecoding signals LAY<4:5>. The third internal decoder 31C receives the internal address signals BAY<6> and BAY<7> in response to the bank select signal CAST and outputs second predecoding signals LAY<6:7>. The fourth internal decoder 31D receives the internal address signal BAY<9> in response to the bank select signal CAST and outputs the third predecoding signal LAY<9>.
Typically, the number of banks in the semiconductor memory devices is four or eight and there is introduced a semiconductor memory devices having 16 banks, recently. The increment of banks in numbers generally causes the increment of the number of main decoders and predecoders. Therefore, with the increment of the number of banks, the circuit size of the main decoder and the predecoder inevitably increases in the semiconductor memory device. If the semiconductor memory device is manufactured with a higher integration, the number of unit cells equipped in one bank also increases. As a result, the circuit size of the main decoder and the predecoder corresponding to each bank more increases with the high integration. Further, the circuit wiring for decoding the address signals increases and this makes it difficult to design the circuit configuration.